News and Features
Practical Power Network Synthesis For Power-Gating Designs
Although methodologies for power network synthesis typically assume that design tools can freely size sleep transistors for power gating, this assumption does not hold up for real-world SoC designs where the sleep transistors are commonly designed as custom switch cells of fixed sizes.
Achieving Certified IP Quality Efficiently
While the increasing use of design intellectual property (IP) has considerably reduced design effort per gate for the chip designer, it has had an inverse effect on the chip-level integration and functional verification effort.
In the Eye of the DFM/DFY Storm
In the case of digital integrated circuits (ICs including ASICs, ASSP, and systems-on-chip), many people seem to have the impression that the transition to the 65 nm technology node is proving to be "not as bad as expected."
Timing Constraints Generation Technology
As design complexity has scaled upward, the need to provide accurate physical constraints like timing, area, power and port locations have become increasingly important.
Leveraging system models for RTL functional verification
Register transfer level (RTL) verification remains the bottleneck in digital hardware design. Industry surveys show that functional verification accounts for 70 percent of the total design effort.
Case study of a complex video system-on-chip
The efficient design of complex, multimedia-intensive, heterogeneous multiprocessing (HMP) systems-on-chip (SoCs) for inclusion in HDTVs and related consumer-oriented systems presents a daunting array of challenges.
Tips for testing outsourced software
One challenge that enterprise organizations face is effectively testing software products developed offshore.
Indian auto developer gains Spice certification
KPIT Cummins, a prominent Indian software company developing automotive electronics and semiconductor products, has been certified at a higher level for using an auto design language.
ASIC design starts to fall 4 percent in 2007, says Gartner
The number of ASIC designs taping out in 2007 looks set to be 3,275 down 4 percent from 3,408 ASIC design start tape outs in 2006, according to market research company Gartner Inc. Of the 2007 ASIC design starts about 200 starts made at 65-nanometer design rules or below.
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Technology News
from EE Times
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AT&T, Verizon Wireless agree to asset swap
AT&T Inc. said Tuesday (Dec. 4) it agreed to swap wireless assets with carrier Verizon Wireless in a deal that would meet divestiture requirements for AT&T's recent $2.8 billion purchase of Dobson Communications Corp.
India's Reliance invests in E-Band Communications
Reliance Technology Ventures, the venture capital arm of the Mumbai-based Reliance ADA Group, has invested an undisclosed amount in E-Band Communications, a San Diego-based designer and manufacturer of multigigabit wireless communication systems.
Tower set to cut costs, jobs
Tower Semiconductor Ltd. (Migdal Haemek, Israel), a small specialty foundry, has initiated a cost-reduction plan that will embrace outsourcing non-core activities and job cuts.
BSEF responds to Greenpeace greener electronics report
The Bromine Science and Environmental Forum (BSEF) reports that the substances environmental group Greenpeace seeks to eliminate, as noted in its recent report "Guide to Greener Electronics" are all approved for use, and provide critical performance and safety functions in a variety of electronic products.
Cellular nets must get smarter, says CTO
Tomorrow's cellular networks will be more intelligent, as they evolve to become more widespread and open.
Gate leakage, down and out?
A high-k dielectric process for CMOS transistors promises to turn the International Semiconductor Roadmap into a freeway by eliminating the gate-leakage problem at advanced nodes down to 10 nanometers.
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