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Standard metric for silicon IP quality emerges
Promising a standard way to evaluate the quality of silicon intellectual property, the Virtual Socket Interface Alliance (VSIA) has created a Quality IP (QIP) Metric that's currently undergoing member review. The QIP Metric consists of spreadsheets with questions that are given relative scores and priorities. The metric was created by the VSIA's VC Quality Development Working Group to provide a standard that will allow both IP creators and integrators to measure the quality of IP against a checklist of critical issues.

Multi-core multi-threaded SoCs pose debugging hurdles
Experienced developers know that good tools support is critical for successful implementation, debugging, and maintenance of embedded products. SoC designs have introduced a new set of problems that make good tools support even more critical. Some problems can be attributed to the inherent decrease in accessibility and visibility for components used in SoC designs; others can be attributed to the increasing complexity of hardware and software. In particular, the increasing use of concurrency in SoC designs will introduce problems that the current generation of tools are not well suited to help debug.

CD-ROMs compile open-source EDA, IP
An updated CD-ROM package contains some 190 open-source EDA tools and 130 hardware designs — all for a price of $25. The package, OpenTech version 1.3.0, is a project of OpenCores, an organization devoted to the development of open-source silicon intellectual property (IP). The OpenTech package is the creation of Jamil Khatib, an FPGA design engineer for Siemens ICT in Rammalla, Palestine. Khatib is one of the founders of the OpenCores web site. All of the tools and designs on the three OpenTech CDs can be freely downloaded from the web, but tracking them all down would take some time and effort.

Arab engineers launch open-source organization
With a goal of bringing open-source "engineering-systems solutions" to Arab nations and the rest of the developing world, three young Arab engineers have launched a volunteer organization called Handasa Arabia, or "Arabic Engineering," dedicated to chip design using open-source silicon intellectual property (IP). The organization is inviting worldwide participation in its projects. Its Web site, which provides information and announcements about open-source hardware, is the launching pad for two ongoing projects: OFOQ, the first Arabic PDA, and Nour, a Bluetooth baseband IP core.

The CEO Interview: Eli Ayalon of DSP Group Inc.
Eli Ayalon, is chairman and chief executive officer of DSP Group Inc., a fabless semiconductor company that has proved itself able to grow profitably even while it has undergone a re-organization and while the rest of the industry has struggled with a downturn. Silicon Strategies: DSP Group was known as the developer of DSP cores available for license but that activity now resides in ParthusCeva. So what is driving your business? Ayalon: Cordless telephony at 900-MHz, 2.4-GHz and 5.8-GHz; this is our traditional area, based on our ability to make voice-signal DSP chips.

RTL design handoff is ready
A significant paradigm shift in design methodology is taking place with RTL design handoff. Shrinking process nodes, increasing SoC design complexities, and tightened purse strings have made the venerable “gate-level design signoff” unacceptable, particularly in light of the wasted time and money associated with synthesis/place-and-route (P&R) design iterations. SoC designers need to operate more efficiently, reduce design costs, and accelerate design turnaround times — and they can accomplish all of these goals by moving more of their design to RTL.

Agere revamps DSP, ARM interface in mobiles
Agere released a messaging interface Tuesday(Aug. 12) that could change the way DSP and ARM microprocessor cores exchange data and control commands in the baseband section of a mobile phone architecture. The baseband processing section of a mobile phone typically houses a DSP core handling Layer 1 processing tasks and an ARM processor handling control functionality. The processor cores rely on AT commands to exchange information. According to Agere, the AT command creates several problems in mobiles, including the lack of parallel processing, an unproven multiplex protocol and the need for non-standard AT commands to control the GPRS engine.

Audio IP market looks for standardization
A 'centre of excellence' for audio intellectual property (IP) brokering has been set up in the UK to supply designers in the automotive, consumer and communication sectors. Sensaura, a developer of audio IP, wants to include third party products as well as its own portfolio. The company's own range includes implementations of discrete algorithms such as Dolby and MPEG decoders through to complete audio IP solutions such as audio watermarking, text-to-speech and voice recognition solutions. Sensaura also wants to share product development risk with its customers through the introduction of a transparent royalty based licensing model.

Linux and DSP code run on a single core
The first Linux port to a multi-threaded processor architecture has been carried out by the Metagence division of Imagination Technologies for its META RISC/DSP processor family. META is a licensable multi-threaded programmable general-purpose processor/DSP intellectual property (IP) core that allows real-time response while supporting efficient multi-function operation. The family provide general purpose processing, complex DSP and multimedia capabilities, real-time operation and reduced power consumption. The processors are being used in a number of consumer products including digital radio and digital TV.

Tezzaron rolls out 'PSiRAM' memory technology
Tezzaron Semiconductor Inc. today (Aug. 18) announced a new and advanced pseudo-static memory technology, built around a 90-nm process technology. The technology, dubbed PSiRAM, is said to enable one of the world's fastest memory devices for system-on-a-chip (SOC) applications. A PSiRAM prototype device boasts 1.3-ns latencies, 1-ns cycle times, and an overall throughput of 2 gigabits-per-second on each pin. The PSiRAM prototype was built in a 90-nm process, producing memory cells measuring only 0.59-square-microns each. Tezzaron intends to license PSiRAM technology for use in SoC applications.

Vendor Announcements
A collection of related vendor press announcements.

Synopsys Releases Synthesizable 6811 Microcontroller
Synopsys, Inc. (Nasdaq: SNPS), the world leader in semiconductor design software, today announced the release of a synthesizable, configurable 6811 8-bit microcontroller into the DesignWare Library. The DesignWare 6811 MacroCell is ideal for designers who need a drop-in, industry-standard embedded 8-bit microcontroller with broad software tool chain support. This solution should also appeal to those designers who are migrating from a discrete 6811 chip to a SoC implementation. The DesignWare 6811 is available to all DesignWare Library licensees at no additional cost, and follows the popular DesignWare 8051 MacroCell, the first 8-bit microcontroller released in the DesignWare Library.

Prosilog and OCP-IP announce a family of OCP compliant AMBA and CORECONNECT bridges
Prosilog SA, the leading provider of innovative solutions for SoC design and verification, and Open Core Protocol International Partnership (OCP-IP) announce the availability of a family of OCP-compliant bridges, for the AMBA and CoreConnect protocols. The bridges support integration and analysis of heterogeneous systems with multiple processors and buses. As a result, for a given OCP compliant IP, Prosilog delivers a configurable adapter, to bridge between the IP and any AMBA or CoreConnect bus.

ARC International Adds Hardware Extensions To Its Processor Core For IPSec Acceleration
ARC International (LSE: ARK), a world leader in user-customizable processors, silicon peripheral IP, real-time operating system and development tools for embedded system design, today introduced its ARCprotect security solution, offering a complete hardware and software security suite to system-on-chip (SoC) designers. The ARCprotect security suite utilizes IP-based hardware extensions to the ARCtangent processor core, as well as ARC's IPShield security software that supports IPSec and IKE security policies. The extensions within the ARCtangent processor enable the acceleration of IPSec algorithms, speeding the processor security algorithms by an order of magnitude.

VSIA Quality Metric Enters Member Review and Beta Testing
The VSI Alliance, an industry association chartered with developing open IP (QIP) Metric is now in member review and member companies have been identified to begin Beta Testing. dress the growing he quality of an IP roup three years ago and was moved into a Development Working Group (DWG) effort eventually headed by Kathy Werner, Mentor standards for System-on-Chip (SoC) development and reuse, today announced that the Quality The QIP Metric was created by VSIA's VC Quality Development Working Group (DWG) to adneed for a standard that would allow both the designer of the IP and the IP integrator to measure tcore against a checklist of critical issues.

Vendor Design Notes
A collection of related vendor datasheets, application notes and white papers.

Addressing the Layout Challenges of Increasing Analog Content in SoCs
from Mentor Graphics
The growing complexity and functionality of SoC designs is increasing the quantity of analog blocks on SoC chips. End user applications, including video cell phones, MP3 music devices and more complex wire-less devices such as web browsers and PDAs are demanding broader functionality on single devices. This demand for increasingly diverse capabilities on a single device, combined with the drive for longer battery life, lower power consumption and smaller sizes has driven the development of mixed-signal devices on a single chip. By 2006 it is estimated that 75% of all SoC designs will contain some analog blocks. This demand is forcing design teams, both digital and analog, to incorporate foreign blocks into their design.

Project: CF Reconfigurable Computing Array
from opencores.org
Cores are generated from Confluence; a modern logic design language developed by Launchbird Design Systems. Confluence is a simple, yet highly expressive language that compiles into Verilog, VHDL, C, and Python. The Reconfigurable Computing Array (RCA) is a platform for dynamic reconfigurable computing. RCA consists of a fine-grained array of reconfigurable "square" logic tiles. Similar to an FPGA CLB, a tile can be programmed to perform a wide variety of functions.

DW_6811 datasheet
from Synopsys
The DesignWare 6811 MacroCell (DW_6811) is a high-performance, synthesizable and configurable 8-bit microcontroller designed for fast and easy integration into SoC, ASIC, or FPGA designs. The technology-independent DW_6811 MacroCell is fully binary compatible with the industry standard 6811 microcontrollers and includes a complete verification environment. To ensure ease of use, this powerful solution is packaged with Synopsys' coreConsultant tool, a user-friendly wizard, which walks the designer through the necessary steps of core integration, including configuration, simulation, and synthesis.

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